VTSS Does Not Trip From Driver's Front Door
- Open driver's front door. Using scan tool, select BODY, DOOR MODULES then INPUT/OUTPUT. Read DRV DOOR AJAR SW status. If status is CLOSED, go to next step. If status is not CLOSED, go to step 3.
- Close driver's front door. Read DRV DOOR AJAR SW status. If status is CLOSED, replace BCM. See BODY CONTROL MODULE under REMOVAL & INSTALLATION. Perform VEHICLE THEFT SECURITY SYSTEM VERIFICATION TEST under VERIFICATION TESTS. If status is not CLOSED, replace Driver's Door Module (DDM). See appropriate POWER WINDOWS article. Perform VEHICLE THEFT SECURITY SYSTEM VERIFICATION TEST under VERIFICATION TESTS.
- Remove driver's front door inner trim panel. Disconnect driver's door lock motor/ajar switch connector. Connect a jumper wire between driver's door lock motor/ajar switch connector terminals No. 1 (Tan/Red wire) and No. 2 (Black wire). See Figure. Read DRV DOOR AJAR SW status. If status is not CLOSED, go to next step. If status is CLOSED, replace driver's door lock motor/ajar switch. See appropriate POWER DOOR LOCKS article. Perform VEHICLE THEFT SECURITY SYSTEM VERIFICATION TEST under VERIFICATION TESTS.
- Using DVOM, measure resistance between driver's door lock motor/ajar switch connector terminal No. 2 (Black wire) and ground. If resistance is less than 5 ohms, go to next step. If resistance is greater than 5 ohms, repair open in Black wire between driver's door lock motor/ajar switch and ground. Perform VEHICLE THEFT SECURITY SYSTEM VERIFICATION TEST under VERIFICATION TESTS.
- Disconnect Driver's Door Module (DDM) connector C1. Using DVOM, measure resistance of Tan/Red wire between DDM connector C1 terminal No. 11 and driver's door lock motor/ajar switch connector terminal No. 1. See Figure. If resistance is less than 5 ohms, go to next step. If resistance is greater than 5 ohms, repair open in Tan/Red wire. Perform VEHICLE THEFT SECURITY SYSTEM VERIFICATION TEST under VERIFICATION TESTS.
- Replace DDM. See appropriate POWER WINDOWS article. Perform VEHICLE THEFT SECURITY SYSTEM VERIFICATION TEST under VERIFICATION TESTS.